Digital Logic Gates, From One Bit to a Counter
After reading this you will be able to trace a signal through any gate, predict what a circuit outputs before you wire it, and understand why some feedback loops store a bit while others oscillate forever.
What a logic gate actually is
A digital circuit works with exactly two voltage levels. The simulator draws them as 0 and 1, and a wire carrying a 1 glows green. Every gate is a small fixed rule that turns one or two input bits into one output bit.
Take the AND gate. It outputs 1 only when both inputs are 1. Wire two input switches into an AND gate and an LED onto its output. Flip both switches on and the LED lights. Flip either one off and it goes dark. That is the whole gate: four possible inputs, four fixed answers.
Seven gates cover almost everything you will build. Here is each one for two inputs a and b.
| a | b | AND | OR | XOR | NAND |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 | 1 |
| 1 | 1 | 1 | 1 | 0 | 0 |
NOT takes one input and flips it: 0 becomes 1. NOR is OR followed by NOT, so it outputs 1 only when both inputs are 0. XNOR is XOR followed by NOT, so it outputs 1 when the two inputs match.
When to reach for the simulator
Use it when you want to see cause and effect one wire at a time. It is built for learning: a half adder has 3 gates, a full adder has about 5, and you can watch each output change the instant you flip a switch.
It is not built for large designs. Once you cross a few dozen gates the grid gets crowded and tracing signals by eye stops being useful. For minimizing a boolean function of four or five variables, the Karnaugh Map Minimizer will give you a smaller circuit than hand-wiring ever will. Use the K-map to find the equation, then build that equation here to confirm it.
Build a circuit, run the truth-table generator, then feed the same truth table into the K-map minimizer. If the minimized equation produces the same table, your circuit is correct and probably too big.
The math: boolean algebra behind the wires
Every combinational circuit (one with no feedback and no clock) computes a boolean function. You can write it as an equation. AND is a product, OR is a sum, and NOT is an overbar.
These two equations are the half adder. S is the sum bit, computed by XOR (written \oplus). C is the carry bit, computed by AND (written as a product a \cdot b). Read it in plain words: the sum is 1 when exactly one input is 1, and the carry is 1 only when both are.
Why XOR for the sum? Adding two single bits in binary gives 0+0=0, 0+1=1, 1+0=1, and 1+1=10. The low bit of those four results is 0, 1, 1, 0, which is exactly XOR. The high bit is 0, 0, 0, 1, which is exactly AND. The gates were not chosen by taste; they fall out of the arithmetic.
A worked example: the full adder preset
A half adder cannot handle a carry coming in from a lower bit. The full adder fixes that. It has three inputs, a, b, and carry-in C_{in}, and two outputs, sum S and carry-out C_{out}.
The sum is 1 when an odd number of the three inputs are 1. The carry-out is 1 when at least two of the three inputs are 1:
Here + is OR and \cdot is AND. The carry-out is 1 if a and b are both 1, or if the carry-in is 1 and exactly one of a, b is 1.
Load the full adder preset and check every row
- Load the full adder preset. You will see two XOR gates chained for
S, two AND gates, and one OR gate for C_{out}. - Set
a=1,b=1, C_{in}=0. The first XOR outputs0, soS=0. The AND ofaandbis1, so C_{out}=1. That reads as binary10, decimal 2, which is1+1+0. Correct. - Set all three to
1. Three ones is odd, soS=1. At least two are1, so C_{out}=1. That reads as11, decimal 3, which is1+1+1. Correct.
| a | b | Cin | S | Cout | decimal |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | 1 | 2 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 2 |
| 1 | 1 | 0 | 0 | 1 | 2 |
| 1 | 1 | 1 | 1 | 1 | 3 |
Read the decimal column: it is always the number of input ones, from 0 to 3, written in two-bit binary as C_{out}S. That is the full adder doing its one job.
Feedback, memory and oscillation
Combinational circuits have no memory: the same inputs always give the same outputs. The moment you wire an output back to an earlier input, the circuit can remember. The simplest memory is two cross-coupled NAND gates, the SR latch.
Each NAND feeds the other. With both control inputs held at 1, the loop has two stable states: Q=1 or Q=0. It holds whichever one it was last pushed into. That single stored bit lives entirely in the feedback loop, with no clock. This is the origin of every static RAM cell.
The simulator resolves feedback by running repeated relaxation passes until nothing changes. A latch has an even number of inversions around the loop (two NANDs), so it settles. Wire a single NOT gate's output back to its own input and you have one inversion: the output must be both the opposite of itself and equal to itself. No stable state exists, so the simulator flags it as oscillating rather than pretending to freeze on a value.
A NAND SR latch has one forbidden input: both control inputs at 0 drive both outputs to 1, so Q and \bar{Q} are no longer opposites. Release both at once and the settled state is unpredictable. Real designs avoid this input on purpose.
Clocks, flip-flops and counting
A latch reacts continuously. A D flip-flop reacts only at one instant: the rising edge of its clock, when the clock goes from 0 to 1. At that edge it copies input D to output Q and holds it until the next rising edge. Between edges, changing D does nothing.
This gives you a frequency divider. Wire \bar{Q} back to D. At every rising edge the flip-flop loads the opposite of its current output, so Q flips once per clock rise. Two clock rises produce one full Q cycle, so Q runs at half the clock frequency.
Chain four flip-flops, each clocked by the previous stage's output, and you get the 4-bit ripple counter preset. Stage 0 divides by 2, stage 1 by 4, stage 2 by 8, stage 3 by 16. Read the four Q outputs as a binary number and it counts 0, 1, 2, ..., 15, then wraps back to 0. It is called a ripple counter because each edge propagates up the chain one stage at a time. To see how ordered data structures step through their states in a similar way, try the Data Structure Visualizer.
Common mistakes
Three errors account for most confusion when a circuit does not behave.
- Confusing NAND with AND (and NOR with OR)
- The bubble on the output inverts. NAND outputs
0only when both inputs are1, the exact opposite of AND. If your output looks upside down, check the bubble. - Expecting a truth table from a clocked circuit
- The truth-table generator sweeps every input combination and reads the outputs. That only makes sense when outputs depend on inputs alone. A flip-flop's output depends on its history, so the generator refuses clocked circuits and caps at 6 switches, which is 64 rows.
- Leaving an input floating
- An unconnected gate input has no defined value. Wire every input to a switch or another output. A half adder with only one switch connected will not produce a meaningful sum.
Related tools
Once you have a truth table, minimize it on the Karnaugh Map Minimizer to find the smallest gate count. If you want to see why binary arithmetic breaks for fractions, the IEEE-754 Floating Point Explorer shows the bit patterns directly. For the memory hierarchy that sits above these gates in a real machine, the Cache Replacement Simulator animates how a cache decides what to keep.
Frequently asked questions
Why does one wire glow green and another stay dark?
Green means the wire currently carries a 1. Dark means 0. The colours update live, so flipping an input switch shows you exactly which downstream wires change.
Can I build any circuit from just NAND gates?
Yes. NAND is functionally complete: you can build NOT (tie both inputs together), AND (NAND then NOT), OR, and everything else from NAND alone. NOR is also complete on its own. This is why chip makers can build entire processors from one repeated gate type.
Why does my NOT-gate loop say oscillating instead of giving an answer?
A loop with an odd number of inversions has no stable state: the value must equal its own opposite. The simulator runs relaxation passes and, when the value keeps flipping, flags it as oscillating rather than freezing on a false result. Latches work because they have an even inversion count.
How many inputs can the truth-table generator handle?
Up to 6 switches, giving 2^6 = 64 rows. The cap keeps generation instant. It works only on clock-free combinational circuits.
What is the difference between a latch and a flip-flop?
A latch is level-sensitive: it follows its inputs whenever its enable is active. A flip-flop is edge-triggered: it samples its input only at the instant the clock rises. Flip-flops are what let you build counters that advance exactly once per clock tick.
Related tools
Bloom Filter Playground
Add items, watch bits light up, measure the false positive rate.
Cache Replacement Simulator
Animate FIFO, LRU, LFU, CLOCK, ARC and Bélády's OPT on any access sequence.
Consistent Hashing Ring
See why adding a server moves 1/N of the keys, not all of them.
Data Structure Visualizer
Watch BST, AVL, red-black trees, heaps, hash tables, tries and union-find work, step by step.
Git Branching Sandbox
Type git commands and watch the commit DAG, branches and HEAD move — with levels, remotes, undo, and merge-vs-rebase contrast.
IEEE-754 Floating Point Explorer
Flip the bits of a float and see why 0.1 + 0.2 ≠ 0.3.